library ieee;
use ieee.std_logic_1164.all;

entity digital_show is
    port(counter_time: in std_logic_vector(3 downto 0);
         en: in std_logic;
         seven_seg_input: out std_logic_vector(7 downto 0));
end digital_show;

architecture behave of digital_show is
    signal counter_time_input: std_logic_vector(4 downto 0);
    signal seven_seg_input_reg: std_logic_vector(7 downto 0);
begin
    counter_time_input <= en & counter_time;
    display:process(counter_time_input, seven_seg_input_reg)
    begin
        case counter_time_input is
            when "00000" => seven_seg_input_reg <= "00000010";
            when "00001" => seven_seg_input_reg <= "10011110";
            when "00010" => seven_seg_input_reg <= "10011110";
            when "00011" => seven_seg_input_reg <= "10011110";
            when "00100" => seven_seg_input_reg <= "10011110";
            when "00101" => seven_seg_input_reg <= "10011110";
            when "00110" => seven_seg_input_reg <= "10011110";
            when "00111" => seven_seg_input_reg <= "10011110";
            when "01000" => seven_seg_input_reg <= "10011110";
            when "01001" => seven_seg_input_reg <= "10011110";
            when others => seven_seg_input_reg <= "11111111";
        end case;
        seven_seg_input <= seven_seg_input_reg;
    end process;
end behave;
